/*****************************************************************************
 *                                                                           *
 * Module:       Seven_Segment_Display                                       *
 * Description:                                                              *
 *      This module writes data to Seven Segment Displays.                   *
 *                                                                           *
 *****************************************************************************/

module Seven_Segment_Display (
	// Inputs
	clk,
	reset_n,
	
	register_0,
	register_1,
	register_2,
	register_3,

	register_selection,

	// Bidirectionals

	// Outputs
	seven_segment_display_0,
	seven_segment_display_1,
	seven_segment_display_2,
	seven_segment_display_3,
	seven_segment_display_4,
	seven_segment_display_5,
	seven_segment_display_6,
	seven_segment_display_7
);


/*****************************************************************************
 *                           Parameter Declarations                          *
 *****************************************************************************/


/*****************************************************************************
 *                             Port Declarations                             *
 *****************************************************************************/
// Inputs
input				clk;
input				reset_n;

input		[15:0]	register_0;
input		[15:0]	register_1;
input		[15:0]	register_2;
input		[15:0]	register_3;

input		[1:0]	register_selection;

// Bidirectionals

// Outputs
output		[6:0]	seven_segment_display_0;
output		[6:0]	seven_segment_display_1;
output		[6:0]	seven_segment_display_2;
output		[6:0]	seven_segment_display_3;
output		[6:0]	seven_segment_display_4;
output		[6:0]	seven_segment_display_5;
output		[6:0]	seven_segment_display_6;
output		[6:0]	seven_segment_display_7;

/*****************************************************************************
 *                 Internal Wires and Registers Declarations                 *
 *****************************************************************************/

// Internal Wires
reg [15:0] result;

// Internal Registers

// State Machine Registers

/*****************************************************************************
 *                         Finite State Machine(s)                           *
 *****************************************************************************/


/*****************************************************************************
 *                             Sequential Logic                              *
 *****************************************************************************/
always @(posedge clk)
begin
	if (reset_n == 0)
		result = 0;
	else
	begin
	case(register_selection)
		0:result = register_0;
		1:result = register_1;
		2:result = register_2;
		3:result = register_3;
	endcase
	end
end


/* Multiplication result goes to HEX displays. */
hex_digits h0 (result[3:0], seven_segment_display_0);
hex_digits h1 (result[7:4], seven_segment_display_1);
hex_digits h2 (result[11:8], seven_segment_display_2);
hex_digits h3 (result[15:12], seven_segment_display_3);
//hex_digits h4 (result[19:16], seven_segment_display_4);
//hex_digits h5 (result[23:20], seven_segment_display_5);
//hex_digits h6 (result[27:24], seven_segment_display_6);
//hex_digits h7 (result[31:28], seven_segment_display_7);

/*****************************************************************************
 *                            Combinational Logic                            *
 *****************************************************************************/


/*****************************************************************************
 *                              Internal Modules                             *
 *****************************************************************************/


endmodule

